Only Buffer When You Need To: Reducing On-chip GPU Traffic with Reconfigurable Local Atomic Buffers

Only Buffer When You Need To: Reducing On-chip GPU Traffic with Reconfigurable Local Atomic Buffers

BACKGROUND

GPU	Feature Configuration (Size, Access Latency)
SMs	80
# Registers / SM	64 KB
LI Instruction Cache / SM	128 KB
LI Data Cache / SM	32 KB (max 128 KB), 28 cycles

GPU	Feature Configuration (Size, Access Latency)
L2 Cache	4.6 MB, 148 cycles
MSHR	256 (L1) and 192 (L2) Entries
Shared Memory Size / SM	96 KB (max 128 KB), 19 cycles
Memory	16 GB HBM2, 248 cycles